In a computer system, a small amount of fast cache memory is typically provided separately from the main memory. Multiple levels of cache memory are provided, in order to cut back on accessing the main memory when a cache miss occurs. For example, a secondary cache that can be accessed faster than the main memory may be provided between the primary cache and the main memory.
In the related art, technology for speeding up data transfers with the CPU is realized by a main memory operating in accordance with a standard referred to as Double Data Rate 2 (DDR2). DDR2 is a technique that utilizes both the rising edge and falling edge of a clock signal when synchronizing respective circuits inside a computer. According to DDR2, the processing efficiency per unit time can be increased by a factor of two as compared to the case of synchronizing respective circuit by using only the rising edges or only the falling edges of the clock. In the DDR2 standard, the smallest unit of memory access is 64 bytes. In accordance with this value, the data size stored in the cache memory (the line size) is likewise set to 64 bytes to match the smallest unit of memory access with respect to the main memory.
Technology related to cache memory is disclosed in Japanese Unexamined Patent Application Publication No. 2002-278836, for example.
Meanwhile, a standard referred to as DDR3 has come into use as the third generation of DDR. Although the internal and external frequency ratio with respect to the main memory is the same as DDR2, the internal data size read from the main memory in a single cycle in DDR3 has been doubled to 128 bytes. In order to bring out the fullest potential of such DDR3, it is necessary to access the main memory at double the data size of DDR2.
As described above, if the main memory is accessed in units of 128 bytes while the cache memory line size remains at 64 bytes similarly to DDR2, then cache coherency control becomes complicated. Cache coherency control refers to processes for synchronizing recording information in the main memory with recorded information in the cache memory. Therefore, it is conceivable to expand the line size of the cache system to 128 bytes, the same number of bytes used when accessing the main memory.
However, if the line size of the cache system is expanded by a factor of two, it takes twice the number of cycles to register data in the cache memory or move out data on a line to be replaced. As the number of cache registration and move out processes increases, the pipeline becomes increasingly dominated by registration and move out processes for the cache memory. As a result, processes for reading and writing data with respect to the cache memory become less frequent on the pipeline.